1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device, and in particular, to a lamination-type NAND flash memory.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although the dimension for each device must be reduced (refinement) to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage are scaled.
Therefore, various measures have been considered recently to achieve a higher integration density of memory devices. For example, these measures include configurations such as using a multi-value technology, laminating memory cells in a three-dimensional manner (see, Japanese Patent Laid-Open No. 2007-317874), and using MEMS (Micro Electro Mechanical Systems).
However, for the configuration of laminating memory cells in a three-dimensional manner, some difference in height is involved between transistors that form a memory cell part and others that are formed on the same substrate and configure a peripheral circuit part. Accordingly, this would cause a difference in depth of focus in exposure, which may result in the upper portion of the memory cell part dishing in Chemical Mechanical Polishing, residual films being left on the top surface of the peripheral circuit part, and so on, leading to unstable operation of the manufactured products.
Therefore, in the prior art, it is difficult to provide lamination-type non-volatile semiconductor storage devices with stable operation.